[
  {
    "EventCode": "0x00",
    "UMask": "0x01",
    "EventName": "INST_RETIRED.ANY",
    "BriefDescription": "Counts the number of instructions retired. (Fixed event)",
    "PublicDescription": "Counts the number of instructions that retire. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers.  This event uses fixed counter 0.",
    "Counter": "32",
    "PEBScounters": "32",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "Errata": "0",
    "Offcore": "0",
    "PDIR_COUNTER": "0"
  },
  {
    "EventCode": "0x00",
    "UMask": "0x02",
    "EventName": "CPU_CLK_UNHALTED.CORE",
    "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)",
    "PublicDescription": "Counts the number of core cycles while the core is not in a halt state.  The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time.  This event uses fixed counter 1.",
    "Counter": "33",
    "PEBScounters": "33",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "Errata": "0",
    "Offcore": "0",
    "PDIR_COUNTER": "na"
  },
  {
    "EventCode": "0x00",
    "UMask": "0x03",
    "EventName": "CPU_CLK_UNHALTED.REF_TSC",
    "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event)",
    "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction.  The core frequency may change from time.  This event is not affected by core frequency changes and at a fixed frequency.  This event uses fixed counter 2.",
    "Counter": "34",
    "PEBScounters": "34",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "Errata": "0",
    "Offcore": "0",
    "PDIR_COUNTER": "na"
  },
  {
    "EventCode": "0x08",
    "UMask": "0x02",
    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
    "BriefDescription": "Counts the number of completed page walks due to a demand load DTLB miss to a 4K page.",
    "PublicDescription": "Counts the number of page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 4K pages.  The page walks can end with or without a page fault.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "Errata": "0",
    "Offcore": "0",
    "PDIR_COUNTER": "na"
  },
  {
    "EventCode": "0x08",
    "UMask": "0x04",
    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
    "BriefDescription": "Counts the number of completed page walks due to a demand load DTLB miss to a 2M or 4M page.",
    "PublicDescription": "Counts the number of completed page walks due to a demand load (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 2M or 4M pages.  The page walks can end with or without a page fault.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "Errata": "0",
    "Offcore": "0",
    "PDIR_COUNTER": "na"
  },
  {
    "EventCode": "0x2e",
    "UMask": "0x41",
    "EventName": "LONGEST_LAT_CACHE.MISS",
    "BriefDescription": "Counts the number of memory requests that miss in the last level cache. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2 cache.  Counts on a per core basis.",
    "PublicDescription": "Counts the number of memory requests that miss in the last level cache. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2 cache.  Counts on a per core basis.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "Errata": "0",
    "Offcore": "0",
    "PDIR_COUNTER": "na"
  },
  {
    "EventCode": "0x2e",
    "UMask": "0x4f",
    "EventName": "LONGEST_LAT_CACHE.REFERENCE",
    "BriefDescription": "Counts the number of memory requests that reference a cache line in the last level cache. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2 cache.  Counts on a per core basis.",
    "PublicDescription": "Counts cacheable memory requests that access the Last Level Cache.  Requests include Demand Loads, Reads for Ownership(RFO), Instruction fetches and L1 HW prefetches. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "Errata": "0",
    "Offcore": "0",
    "PDIR_COUNTER": "na"
  },
  {
    "EventCode": "0x3c",
    "UMask": "0x00",
    "EventName": "CPU_CLK_UNHALTED.CORE_P",
    "BriefDescription": "Counts the number of unhalted core clock cycles.",
    "PublicDescription": "Counts the number of core cycles while the core is not in a halt state.  The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time.  This event uses a programmable general purpose performance counter.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "Errata": "0",
    "Offcore": "0",
    "PDIR_COUNTER": "na"
  },
  {
    "EventCode": "0x3c",
    "UMask": "0x01",
    "EventName": "CPU_CLK_UNHALTED.REF",
    "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.",
    "PublicDescription": "Counts reference cycles (at TSC frequency) when core is not halted.  This event uses a programmable general purpose perfmon counter.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "Errata": "0",
    "Offcore": "0",
    "PDIR_COUNTER": "na"
  },
  {
    "EventCode": "0x49",
    "UMask": "0x02",
    "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
    "BriefDescription": "Counts the number of page walks completed due to a demand data store to a 4K page.",
    "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages.  The page walks can end with or without a page fault.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "Errata": "0",
    "Offcore": "0",
    "PDIR_COUNTER": "na"
  },
  {
    "EventCode": "0x49",
    "UMask": "0x04",
    "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
    "BriefDescription": "Counts the number of page walks completed due to a demand data store to a 2M or 4M page.",
    "PublicDescription": "Counts the number of page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M or 4M pages.  The page walks can end with or without a page fault.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "Errata": "0",
    "Offcore": "0",
    "PDIR_COUNTER": "na"
  },
  {
    "EventCode": "0x71",
    "UMask": "0x00",
    "EventName": "TOPDOWN_FE_BOUND.ALL",
    "BriefDescription": "Counts the number of retirement slots not consumed due to front end stalls",
    "PublicDescription": "tbd",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "Errata": "0",
    "Offcore": "0",
    "PDIR_COUNTER": "na"
  },
  {
    "EventCode": "0x73",
    "UMask": "0x06",
    "EventName": "TOPDOWN_BAD_SPECULATION.ALL",
    "BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to Fast Nukes such as MOnukes are counted. Other nukes are not accounted for.",
    "PublicDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.  Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the IQ. Also, includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "Errata": "0",
    "Offcore": "0",
    "PDIR_COUNTER": "na"
  },
  {
    "EventCode": "0x74",
    "UMask": "0x00",
    "EventName": "TOPDOWN_BE_BOUND.ALL",
    "BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls",
    "PublicDescription": "tbd",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "Errata": "0",
    "Offcore": "0",
    "PDIR_COUNTER": "na"
  },
  {
    "EventCode": "0x80",
    "UMask": "0x02",
    "EventName": "ICACHE.MISSES",
    "BriefDescription": "Counts the number of requests to the Instruction Cache (ICache) for one or more bytes in a cache line that do not hit in the ICache (miss).",
    "PublicDescription": "Counts requests to the Instruction Cache (ICache)  for one or more bytes in an ICache Line and that cache line is not in the ICache (miss).  The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS.  Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "Errata": "0",
    "Offcore": "0",
    "PDIR_COUNTER": "na"
  },
  {
    "EventCode": "0x80",
    "UMask": "0x03",
    "EventName": "ICACHE.ACCESSES",
    "BriefDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes cache Line.",
    "PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line.  The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS.  Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "Errata": "0",
    "Offcore": "0",
    "PDIR_COUNTER": "na"
  },
  {
    "EventCode": "0x81",
    "UMask": "0x04",
    "EventName": "ITLB.FILLS",
    "BriefDescription": "Counts the number of times there was an ITLB miss and a new translation was filled into the ITLB.",
    "PublicDescription": "Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) and new translation was filled into the ITLB.  The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "Errata": "0",
    "Offcore": "0",
    "PDIR_COUNTER": "na"
  },
  {
    "EventCode": "0x85",
    "UMask": "0x02",
    "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
    "BriefDescription": "Page walk completed due to an instruction fetch in a 4K page.",
    "PublicDescription": "Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 4K pages.  The page walks can end with or without a page fault.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "Errata": "0",
    "Offcore": "0",
    "PDIR_COUNTER": "na"
  },
  {
    "EventCode": "0x85",
    "UMask": "0x04",
    "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
    "BriefDescription": "Page walk completed due to an instruction fetch in a 2M or 4M page.",
    "PublicDescription": "Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 2M or 4M pages.  The page walks can end with or without a page fault.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "Errata": "0",
    "Offcore": "0",
    "PDIR_COUNTER": "na"
  },
  {
    "EventCode": "0xc0",
    "UMask": "0x00",
    "EventName": "INST_RETIRED.ANY_P",
    "BriefDescription": "Counts the number of instructions retired.",
    "PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers.  This is an architectural performance event.  This event uses a Programmable general purpose perfmon counter. *This event is Precise Event capable:  The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "Errata": "0",
    "Offcore": "0",
    "PDIR_COUNTER": "0"
  },
  {
    "EventCode": "0xc2",
    "UMask": "0x00",
    "EventName": "TOPDOWN_RETIRING.ALL",
    "BriefDescription": "Count the number of uops retired",
    "PublicDescription": "Count the number of uops retired",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "Errata": "0",
    "Offcore": "0",
    "PDIR_COUNTER": "0"
  },
  {
    "EventCode": "0xc3",
    "UMask": "0x00",
    "EventName": "MACHINE_CLEARS.ANY",
    "BriefDescription": "Counts all machine clears due to, but not limited to memory ordering, memory disambiguation, SMC, page faults and FP assist.",
    "PublicDescription": "Counts all machine clears due to, but not limited to memory ordering, memory disambiguation, SMC, page faults and FP assist.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "20003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "Errata": "0",
    "Offcore": "0",
    "PDIR_COUNTER": "na"
  },
  {
    "EventCode": "0xc4",
    "UMask": "0x00",
    "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
    "BriefDescription": "Counts the number of branch instructions retired for all branch types.",
    "PublicDescription": "Counts branch instructions retired for all branch types. This event is Precise Event capable. This is an architectural event.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "Errata": "0",
    "Offcore": "0",
    "PDIR_COUNTER": "0"
  },
  {
    "EventCode": "0xc5",
    "UMask": "0x00",
    "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
    "BriefDescription": "Counts the number of mispredicted branch instructions retired.",
    "PublicDescription": "Counts the number of mispredicted branch instructions retired for all branch types. This event is Precise Event capable. This is an architectural event.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "Errata": "0",
    "Offcore": "0",
    "PDIR_COUNTER": "0"
  },
  {
    "EventCode": "0xcd",
    "UMask": "0x00",
    "EventName": "CYCLES_DIV_BUSY.ANY",
    "BriefDescription": "Counts cycles the floating point divider or integer divider or both are busy.  Does not imply a stall waiting for either divider.",
    "PublicDescription": "Counts cycles the floating point divider or integer divider or both are busy.  Does not imply a stall waiting for either divider.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "Errata": "0",
    "Offcore": "0",
    "PDIR_COUNTER": "na"
  },
  {
    "EventCode": "0xd0",
    "UMask": "0x81",
    "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
    "BriefDescription": "Counts the number of load uops retired.",
    "PublicDescription": "Counts the number of load uops retired. This event is Precise Event capable",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "Errata": "0",
    "Offcore": "0",
    "PDIR_COUNTER": "0"
  },
  {
    "EventCode": "0xd0",
    "UMask": "0x82",
    "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
    "BriefDescription": "Counts the number of store uops retired.",
    "PublicDescription": "Counts the number of store uops retired. This event is Precise Event capable",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "Errata": "0",
    "Offcore": "0",
    "PDIR_COUNTER": "0"
  },
  {
    "EventCode": "0xd1",
    "UMask": "0x01",
    "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
    "BriefDescription": "Counts the number of load uops retired that hit the level 1 data cache",
    "PublicDescription": "Counts the number of load uops retired that hit the level 1 data cache",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "Errata": "0",
    "Offcore": "0",
    "PDIR_COUNTER": "0"
  },
  {
    "EventCode": "0xd1",
    "UMask": "0x02",
    "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
    "BriefDescription": "Counts the number of load uops retired that hit in the level 2 cache",
    "PublicDescription": "Counts the number of load uops retired that hit in the level 2 cache",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "Errata": "0",
    "Offcore": "0",
    "PDIR_COUNTER": "0"
  },
  {
    "EventCode": "0xd1",
    "UMask": "0x04",
    "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
    "BriefDescription": "Counts the number of load uops retired that miss in the level 3 cache",
    "PublicDescription": "Counts the number of load uops retired that miss in the level 3 cache",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "Errata": "0",
    "Offcore": "0",
    "PDIR_COUNTER": "0"
  },
  {
    "EventCode": "0xd1",
    "UMask": "0x08",
    "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
    "BriefDescription": "Counts the number of load uops retired that miss in the level 1 data cache",
    "PublicDescription": "Counts the number of load uops retired that miss in the level 1 data cache",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "Errata": "0",
    "Offcore": "0",
    "PDIR_COUNTER": "0"
  },
  {
    "EventCode": "0xd1",
    "UMask": "0x10",
    "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
    "BriefDescription": "Counts the number of load uops retired that miss in the level 2 cache",
    "PublicDescription": "Counts the number of load uops retired that miss in the level 2 cache",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "Errata": "0",
    "Offcore": "0",
    "PDIR_COUNTER": "0"
  },
  {
    "EventCode": "0XB7",
    "UMask": "0x01,0x02",
    "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
    "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE",
    "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x1a6,0x1a7",
    "MSRValue": "0x0000000000010001",
    "CollectPEBSRecord": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "Errata": "null",
    "Offcore": "1",
    "PDIR_COUNTER": "0"
  },
  {
    "EventCode": "0XB7",
    "UMask": "0x01,0x02",
    "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
    "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS",
    "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x1a6,0x1a7",
    "MSRValue": "0x0000003F04000001",
    "CollectPEBSRecord": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "Errata": "null",
    "Offcore": "1",
    "PDIR_COUNTER": "0"
  },
  {
    "EventCode": "0XB7",
    "UMask": "0x01,0x02",
    "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
    "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
    "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x1a6,0x1a7",
    "MSRValue": "0x0000000000010002",
    "CollectPEBSRecord": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "Errata": "null",
    "Offcore": "1",
    "PDIR_COUNTER": "0"
  },
  {
    "EventCode": "0XB7",
    "UMask": "0x01,0x02",
    "EventName": "OCR.DEMAND_RFO.L3_MISS",
    "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
    "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x1a6,0x1a7",
    "MSRValue": "0x0000003F04000002",
    "CollectPEBSRecord": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "Errata": "null",
    "Offcore": "1",
    "PDIR_COUNTER": "0"
  }
]